CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

CVSS v3 6.5 MEDIUM

6.5^/10

CVSS v3 : MEDIUM

Vector :

Exploitability : 2.8 / Impact : 3.6

Attack Vector NETWORK

Attack Complexity LOW

Privileges Required LOW

User Interaction NONE

Confidentiality Impact HIGH

Integrity Impact NONE

Availability Impact NONE

Scope UNCHANGED

References

Link	Resource
https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET	Exploit Third Party Advisory
https://github.com/chipsalliance/rocket-chip.git	Product

Configurations

Configuration 1 (hide)

cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*

History

No history.

Information

Published : 2025-11-10 20:15

Updated : 2026-02-05 15:25

NVD link : CVE-2025-63384

Mitre link : CVE-2025-63384

CVE.ORG link : CVE-2025-63384

JSON object : View

Products Affected

chipsalliance

rocketchip

CWE

CWE-266

Incorrect Privilege Assignment

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